Different types of memory are used in electronic apparatus for various purposes. Read-only memory (ROM) and random-access memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for powering-up an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refresh, making it faster. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants (PDAs).
A typical SRAM device includes an array of addressable memory cells arranged in columns and rows. A typical SRAM cell includes two access transistors and a flip-flop formed with two cross-coupled inverters. Each inverter has a pull-down (driver) and a pull-up (load) transistor. The gates of the access transistors in each row are connected to a word line and the sources of each of the access transistors in each column are connected to either one of a pair of complementary bit lines, BL or BL_. Peripheral circuitry associated with the rows (or word lines) and peripheral circuitry associated with the columns (or bit lines) facilitate reading data from, and writing data to, the SRAM cells.
Generally, to read data from a SRAM cell, a word line driver activates a word line according to an address decoded by a row decoder and received via a control signal path that typically includes an address bus connected to the SRAM device. The access transistors turn on and connect the outputs of the flip-flop to the bit line pair sending control signals representing the data in the SRAM cell to a sense amplifier coupled to the bit line pair. The sense amplifier produces a logical 0 or 1 from the potential difference on the bit line pair, which is, in turn, provided to external circuitry of the associated electronic apparatus, perhaps through a buffer.
As mentioned above, to retain the data written to the SRAM array, each SRAM cell must have a continuous supply of power. SRAM devices, however, are often employed within battery-powered wireless apparatus where power consumption is an important design parameter. Accordingly, SRAM devices are often capable of operating in multiple modes, each mode representing a tradeoff in terms of speed and power consumption. One such mode is the active mode. In the active mode, the SRAM array and surrounding read and write circuitry are provided full power. The array and circuitry are therefore ready for operation at all times, and read and write speed is the fastest. Another mode is the inactive, or sleep, mode. In the inactive mode, the SRAM array is provided power so as not to lose data, but at a reduced voltage to reduce power consumption. In the inactive mode, all of the surrounding read and write circuitry are turned off for maximum power reduction. The surrounding read and write circuitry must be turned back on before reading or writing can occur, and so there is a latency in initiating reading or writing from the inactive mode.
Another mode of operation represents a middle ground between active mode and inactive mode. Retain Till Accessed (RTA) mode calls for the read and write circuitry to remain powered. The SRAM array itself is powered at a reduced voltage sufficient to retain the stored data, but insufficient to allow reliable read or write access. When a read and write access is to be done, only the cells needed for the access are activated; the remaining cells are retained at lower voltage.
Though the RTA mode represents a decrease in latency over the inactive mode, keeping the periphery circuitry powered adds significant power relative to the inactive mode. Furthermore, the stability of the SRAM array may be compromised by voltage mismatches occurring between word line drivers and cells that are activated or deactivated.
Accordingly, what is needed in the art is a way to decrease power in associated periphery circuitry in the RTA mode. More specifically, what is needed in the art is an efficient way to control the voltage of the word line drivers such that they can be reactivated quickly, easily and without introducing substantial voltage mismatches that may compromise SRAM array stability, yet decrease the contribution to power dissipation in the RTA mode.